Source code for Speed Stepper available now

[imported_kriser]

http://www.elevatedstudios.com/pocket/source.htm

I have placed the source with instructions and pretty well commented code up on my website. I didn't put the whole program up, but I though that this would be more useful. The rest of the program is just UI stuff anyway. I will put that up later.

Enjoy

- kriser

[pcguys]

It's nice to see how my beloved ipaq 1910 works behind the scenes.

Thanks!

[rudy1]

cool, thx kriser

I have a question tho. If it isn't to complicated to explain, how do I get the corresponding binary given l, m, n values?

[Silicone Sister]

Intel says more on the subject.


3.4.7 Frequency Change Sequence
The Frequency Change Sequence is used to change the processor clock frequency. During the
Frequency Change Sequence, the CPU, Memory Controller, LCD Controller, and DMA clocks
stop. The other peripheral units continue to function during the Frequency Change Sequence. This
mode is intended to be used to change the frequency from the default condition at initial boot-up. It
may also be used as a power-saving feature used to allow the application processor to run at the
minimum required frequency when the software requires major changes in frequency.

3.4.7.1 Preparing for the Frequency Change Sequence
Software must complete the following steps before it initiates the Frequency Change Sequence:
1. Configure the Memory Controller to ensure SDRAM contents are maintained during the
Frequency Change Sequence. The Memory Controller's refresh timer must be programmed to
match the maximum refresh time associated with the slower of two frequencies (current and
desired). The SDRAM divide by two must be set to a value that prevents the SDRAM
frequency from exceeding the specified frequency. For example, to change from 100/100 to
133/66, the SDRAM bus must be set to divide by two before the frequency change. To change
from 133/66 to 100/100, the SDRAM must be set to one-to-one after the frequency change
sequence is completed. See Section 6, "Memory Controller" for more details.
2. Disable the LCD Controller or configure it to avoid the effects of an interruption in the LCD
clocks and data from the application processor.
3. Configure peripheral units to handle a lack of DMA service for up to 500 ?s. If a peripheral
unit can not function for 500 ?s without DMA service, it must be disabled.
4. Disable peripheral units that can not accommodate a 500 ?s interrupt latency. The interrupts
generated during the Frequency Change Sequence are serviced when the sequence exits.
5. Program the CCCR (Section 3.6.1, "Core Clock Configuration Register") to reflect the desired
frequency.

3.4.7.2 Invoking the Frequency Change Sequence
To invoke the Frequency Change Sequence, software must set FCS in the CCLKCFG (See
Section 3.7.1). When software sets FCS, it may also set or clear other bits in CCLKCFG. If
software sets the TURBO bit in the same write, the CPU enters Turbo Mode when the Frequency
Change Sequence exits.
After software sets the FCS:
1. The CPU clock stops and interrupts to the CPU are gated.
2. The Memory Controller completes all outstanding transactions in its buffers and from the
CPU. New transactions from the LCD or DMA controllers are ignored.
3. The Memory Controller places the SDRAM in self-refresh mode.
Note: Program the Memory Controller to ensure the correct self-refresh time for SDRAM, given the
slower of the current and desired clock frequencies.
3.4.7.3 Behavior During the Frequency Change Sequence
In the Frequency Change Sequence, the processor's PLL clock generator is in the process of
locking to the correct frequency and cannot be used. This means that interrupts cannot be
processed. Interrupts that occur during the Frequency Change Sequence are serviced after the
processor's PLL has locked. The 95.85 MHz and 147.46 MHz PLL clock generators are active and
peripherals, except Memory Controller, LCD Controller, and DMA, may continue to operate
normally, provided they can accommodate the inability to process DMA or Interrupt requests.
DMA or Interrupt requests are not recognized until the Frequency Change Sequence is complete.
The Imprecise Data Abort is also not recognized and if nVDD_FAULT or nBATT_FAULT is
asserted, the assertion is ignored until the Frequency Change Sequence exits. This means that the
processor does not enter Sleep Mode until the Frequency Change Sequence is complete.
3.4.7.4 Completing the Frequency Change Sequence
The Frequency Change Sequence exits when any Reset is asserted. In Hardware and Watchdog
Resets, the Reset entry and exit sequences take precedence over the Frequency Change Sequence
and the PLL resumes in its Reset condition. In GPIO Reset, the Reset exit sequence is delayed
while the PLL relocks and the frequency is set to the desired frequency of the Frequency Change
Sequence.
If the Watchdog Timer is enabled during the Frequency Change Sequence, set the Watchdog Match
Register to ensure that the Frequency Change Sequence completes before the Watchdog Reset is
asserted.
If Hardware or Watchdog Reset is asserted during the Frequency Change Sequence, the DRAM
contents are lost because all states, including Memory Controller configuration and information
about the previous Frequency Change Sequence, are reset. If GPIO Reset is asserted during the
Frequency Change Sequence, the SDRAM contents will be lost during the GPIO Reset exit
sequence if the SDRAM is not in self-refresh mode and the exit sequence exceeds the refresh
interval.
Normally, the Frequency Change Sequence exits in the following sequence:
1. The processor's PLL clock generator is reprogrammed with the desired values, which are in
the CCCR, and begins to relock to those values.
Note: This sequence occurs even if the before and after frequencies are the same.
2. The internal PLL clock generator for the processor clock waits for stabilization. Refer to the
Intelr PXA250 and PXA210 Application Processors Electrical, Mechanical, and Thermal
Specification for details.
3. The CPU clocks restart and the CPU resumes operation at the state indicated by the TURBO
bit (either Run or Turbo Mode). Interrupts to the CPU are no longer gated.
4. The FCS bit is not automatically cleared. To prevent an accidental return to the Frequency
Change Sequence, software must not immediately clear the FCS bit. The bit must be cleared
on the next required write to the register.
5. Values may be written to the CCCR, but they are ignored until the Frequency Change
Sequence is re-entered.
6. The SDRAM must transition out of self-refresh mode and into its idle state. See Section 6,
"Memory Controller" for details on configuring the SDRAM interface.

[imported_kriser]

Originally posted by rudy1
cool, thx kriser

I have a question tho. If it isn't to complicated to explain, how do I get the corresponding binary given l, m, n values?

To put it simply the values act like this

3.6867 * l * m * n = X MHz.

For instance if l = 27, m = 2, n=1.5 then

3.6867 * 27 * 2 * 1.5 = 298.62 MHz

also

3.6867 * 40 * 2 * 1 = 294.9 MHz

Both give around 300 MHz, but the L & n multipliers are different. Changing the L multiplier will change the memory frequency and LCD controller frequency as well as the processor frequency. Changing N will only affect the processor frequency. The only problem with changing N is that the change is temporary. Powering off or resetting will cause that multiplier to be turned off.

Changing N is the safest as it only modifies the processor speed and the XScale has no problem running at 300 MHz. Changing L may have side effects, but other then the screen appearing to darken a bit, I am not sure what else.

[hkfriends]

kriser,

I found some problem in your 0.9 version for 3950 (400MHz)

In untested Feq:
[Turbo Rate]
1. When I select 398, it only go to 354
2. When I select 299, it set back to 398

[Run Rate]
It will have a hanged and need a soft reset.


Do you know what is going on?

Thanks.

[imported_kriser]

Originally posted by hkfriends
kriser,

I found some problem in your 0.9 version for 3950 (400MHz)

In untested Feq:
[Turbo Rate]
1. When I select 398, it only go to 354
2. When I select 299, it set back to 398

[Run Rate]
It will have a hanged and need a soft reset.


Do you know what is going on?

Thanks.

Yea, I have a couple ideas. I think it may be doing what it says, but I may just have things labeled wrong. I will take a look. I don't have access to my development environment right now, but I plan to fix it as soon as I get back.